1.6T Ethernet and Optical Networking: The Complete Guide to the Next Speed Tier for AI Data Centers
What 1.6 terabit Ethernet is, why AI clusters are pulling it forward, how pluggable, linear and co-packaged optics work, what they cost in power, and when deployment scales.
In This Lesson
Build a complete mental model of the 1.6T transition: the electrical lanes and switch silicon underneath it, the optical architecture choices around it, and the practical deployment decisions facing AI-infrastructure teams.
Quick Learning Map
Use these three decisions to understand where 1.6T creates value and which optical design fits the fabric.
Count the bandwidth
Model accelerator, rack and fabric demand to decide where 800G remains enough and where 1.6T removes tiers or links.
Choose the optical boundary
Balance the serviceability of pluggables against the lower power of LPO and the density of CPO.
Validate the system
Test reach, interoperability, thermals, telemetry and failure recovery instead of selecting from port speed alone.
1.6T Ethernet at a Glance
1.6T Ethernet, or 1,600 Gb/s per port, doubles the bandwidth of 800G. It combines 200 Gb/s-per-lane signaling, 224G-class SerDes and 102.4 Tb/s switch ASICs. AI scale-out fabrics are the primary driver, while power and optical reach are the defining engineering constraints.
Key Facts at a Glance
Port speed
1,600 Gb/s, equal to two 800G links or sixteen 100G links.
Lane architecture
Eight lanes at 200 Gb/s per lane using PAM4 modulation.
Electrical interface
224G-class SerDes aligned with OIF CEI-224G work.
Switch silicon
102.4 Tb/s ASICs can expose 64 × 1.6T or 128 × 800G ports.
Module options
OSFP, OSFP-XD and QSFP-DD1600 pluggables, plus co-packaged implementations.
Primary use
AI/ML GPU fabrics, followed by hyperscale spine layers and data-center interconnect.
What Is 1.6T Ethernet?
1.6T Ethernet is the speed grade that carries 1.6 terabits per second on one Ethernet port. It follows the familiar 100G, 200G, 400G and 800G progression, but AI training and inference demand are compressing the normal adoption cycle.
The IEEE 802.3dj generation covers 200G, 400G, 800G and 1.6T operation across electrical interfaces, copper and single-mode fiber at 200 Gb/s per lane. Complementary OIF CEI-224G work defines high-speed electrical interfaces between switch silicon and optics. Together, these efforts provide the basis for interoperable 1.6T equipment.
Inside an AI cluster, the benefit is not simply a larger number on each port. Higher radix and bandwidth can mean fewer physical links, fewer optical modules, fewer switch stages and less serialization delay per bit moved.
Why AI Is Forcing the Jump From 800G to 1.6T
General-purpose cloud growth once set the pace for Ethernet transitions. AI changes that rhythm because network performance directly affects the utilization of expensive accelerators.
GPU bandwidth is outrunning the network
Each accelerator generation connects through faster NICs. When collective operations wait on the fabric, costly GPUs sit idle and cluster economics deteriorate.
Cluster size is exploding
Frontier clusters can span tens of thousands of accelerators. Higher-speed ports can flatten topologies and reduce the number of optics, hops and failure points.
Power is the binding constraint
SerDes and optics consume a meaningful share of fabric power. The design objective is to double bandwidth without doubling watts, which makes optical architecture central.
A 102.4T switch used with 1.6T ports can carry the same aggregate capacity with roughly half as many front-panel links as an 800G design. The exact topology depends on oversubscription, rail optimization, traffic patterns and failure domains, but the direction is clear: more bandwidth per port can simplify the fabric.
The Technology Stack Behind 1.6T
The generational change touches every layer from the electrical lane to the faceplate module and fiber plant.
| Layer | 800G generation | 1.6T generation |
|---|---|---|
| Lane rate | 100 Gb/s per lane (8 × 100G) PAM4 | 200 Gb/s per lane (8 × 200G) PAM4 |
| SerDes | 112G SerDes (CEI-112G) | 224G SerDes (CEI-224G) |
| Switch ASIC | 51.2T, commonly 64 × 800G | 102.4T, commonly 64 × 1.6T or 128 × 800G |
| IEEE generation | 802.3ck / 802.3df | 802.3dj |
| Pluggable forms | OSFP, QSFP-DD800 | OSFP, OSFP-XD, QSFP-DD1600 |
| Optical variants | DR8, 2×FR4, 2×DR4, SR8, VR8 | DR8 at 200G/λ, 2×FR4, 2×DR4, early SR8, LPO and CPO |
| DSP module power | Approximately 14–18 W | Approximately 25–30 W; lower targets with LPO/CPO |
| Passive copper reach | Approximately 2–3 m | Approximately 1–2 m; active copper for longer in-rack links |
The Optical Shift: Pluggable Optics vs LPO vs CPO
At 200 Gb/s per lane, copper reach shrinks and the electrical path between the switch ASIC and the optical engine becomes increasingly expensive in power. Three architectures place that optical boundary in different locations.
DSP-Based Pluggable Optics
A faceplate transceiver uses a digital signal processor to retime and equalize the electrical signal before optical conversion.
- Strengths: hot-swappable, mature, multi-vendor and available across multiple reaches.
- Tradeoffs: the DSP adds power and latency, and many modules create a large thermal load.
- Best fit: multi-vendor fabrics, longer reaches and operational environments that prioritize field replacement.
Linear Pluggable Optics (LPO/LRO)
LPO removes the module DSP and relies on host SerDes equalization. LRO is a partial step that retains more processing on one direction.
- Strengths: lower module power and latency while retaining a replaceable faceplate form.
- Tradeoffs: tighter signal margins, stronger host dependency and generally shorter reach.
- Best fit: controlled, short-reach AI pods with validated switch-to-module combinations.
Co-Packaged Optics (CPO)
CPO places optical engines beside the switch ASIC, leaving only a very short high-speed electrical path before conversion to light.
- Strengths: lowest electrical loss, high density and strong power-per-bit potential.
- Tradeoffs: thermal integration, serviceability and ecosystem or vendor-dependency concerns.
- Best fit: the largest power- and density-constrained AI fabrics.
| Criterion | DSP pluggable | LPO / LRO | CPO |
|---|---|---|---|
| Relative power | Highest | Medium to low | Lowest target |
| Latency | Highest because of DSP retiming | Low | Lowest |
| Serviceability | Excellent, hot-swappable | Excellent, hot-swappable | More limited; designs continue to evolve |
| Interoperability | Strong multi-vendor model | More host-dependent | Mostly platform-specific |
| Reach | Short through long | Short-reach focus | Short to medium |
| Maturity | Shipping | Early deployment | First commercial systems |
Photonics Technologies Enabling 200G Per Lane
Doubling the lane rate is a component-level challenge as much as a standards change. Several technologies work together, and no single one wins every reach and cost point.
Silicon photonics
Integrates modulators, waveguides and detectors on silicon using CMOS-compatible manufacturing. It is important for DR/FR reaches and many CPO designs.
EML lasers
Electro-absorption modulated lasers extend a familiar single-mode approach to higher lane rates, with supply and power challenges at scale.
VCSELs
Low-cost multimode sources remain useful for very short reach, but 200G-per-lane scaling makes the design window tighter.
Thin-film lithium niobate
An emerging modulator platform offering high bandwidth and low drive voltage for future 200G and 400G lanes.
3 nm PAM4 DSPs
More efficient DSP silicon reduces power per bit and helps the serviceable pluggable model survive at 1.6T.
External laser sources
Centralized, replaceable lasers can feed co-packaged optical engines while separating a common failure-prone component from the switch package.
Where 1.6T Fits in the AI Data Center
| Network segment | Role of 1.6T and optical technology |
|---|---|
| Scale-out GPU fabric | The primary target. 1.6T spine ports and 800G/1.6T leaf connectivity can flatten fabrics, while LPO and CPO address power. |
| Scale-up fabric | NVLink, UALink and emerging Ethernet approaches operate inside racks or pods, using overlapping 200G-lane copper and optical-I/O technology. |
| Front-end and storage | Often remains at 400G or 800G until checkpoint, storage and data-loading bandwidth justify the next transition. |
| Data-center interconnect | Coherent 800ZR/ZR+ is established, while 1.6T-class coherent optics extend capacity across distributed AI campuses. |
| Hyperscale cloud spine | Spine and core layers adopt higher speeds first for aggregation efficiency; server access generally moves later. |
1.6T Ethernet vs Other AI Interconnects
1.6T is a physical Ethernet speed, not an entire application transport strategy. It competes with some technologies and supplies the physical layer beneath others.
InfiniBand
Tracks similar lane and aggregate speeds. InfiniBand emphasizes a tightly integrated, deterministic stack, while Ethernet benefits from a broad multi-vendor ecosystem and volume economics.
Ultra Ethernet
UEC is a transport architecture rather than a port speed. It can operate over 800G and 1.6T physical links to make Ethernet better suited to AI workload behavior.
NVLink and UALink
These scale-up technologies serve links within a system, rack or pod. Their protocols differ, even though their cables, SerDes and future optical I/O may share component technology.
Challenges and Open Problems
- Power density: a fully populated 102.4T system with DSP pluggables can push optics and system power into difficult cooling territory.
- 224G signal integrity: PCB traces, packages and connectors become highly loss-sensitive, increasing the use of flyover cables and near-package connections.
- Shrinking copper reach: passive DACs may cover only part of a rack; active electrical cables add power and cost.
- Component supply: 200G optical sources, silicon-photonics capacity and compound-semiconductor supply must grow with AI demand.
- Reliability at scale: tiny lane failure rates become operationally significant across hundreds of thousands of optical channels.
- Standards timing: early products can precede final interoperability maturity, making qualification and firmware lifecycle planning essential.
- CPO serviceability: power savings must be weighed against repair procedures, spare strategy and platform dependency.
Industry Roadmap: 2025 to 2028
These milestones are planning estimates, not guaranteed product dates. Vendor roadmaps, standards work and supply conditions can move independently.
| Period | Expected milestones |
|---|---|
| 2025 | 102.4T switch ASIC announcements and sampling; first 1.6T DSP pluggables and LPO modules; early CPO systems; 800G reaches volume in AI fabrics. |
| 2026 | IEEE 802.3dj completion target; 1.6T-capable NICs with new accelerators; initial hyperscaler and neocloud spine deployments; CPO production at lead customers. |
| 2027 | 1.6T volume ramp; LPO and CPO gain share in AI clusters; early 1.6T coherent DCI; more work on 400G-per-lane components. |
| 2028+ | 3.2T Ethernet standardization, 204.8T switch silicon and optical I/O moving closer to accelerator packages. |
Practical Guidance for Infrastructure Planners
- Design for 1.6T and deploy 800G where it is sufficient. Choose switch platforms, fiber plant and power distribution that support a staged transition.
- Favor single-mode fiber for new high-speed builds. Validate connector and parallel-fiber choices against the selected DR, FR and breakout architectures.
- Budget watts per port. Model optics, ASICs, fans, retimers and cable choices together rather than using only a switch chassis figure.
- Use LPO selectively. It is strongest in controlled, short-reach environments where host SerDes and module combinations are qualified together.
- Treat CPO as a platform decision. Pilot service procedures, external lasers, spares and failure domains along with the power benefit.
- Invest in optical telemetry. Digital diagnostics, link-flap analytics and predictive replacement protect long-running distributed workloads.
- Prove interoperability. Request plug-fest results and run multi-vendor link testing at realistic temperature, reach and error-rate conditions.
1.6T Ethernet Glossary
| Term | Definition |
|---|---|
| 1.6T Ethernet | Ethernet operating at 1.6 terabits per second per port in the IEEE 802.3dj generation. |
| PAM4 | Four-level pulse-amplitude modulation that carries two bits per symbol and supports higher lane rates. |
| SerDes | Serializer/deserializer circuitry that moves data between a chip and high-speed interfaces; 224G-class SerDes underpin 200G lanes. |
| DSP | A digital signal processor inside a transceiver that retimes and equalizes signals, improving margin at the cost of power and latency. |
| LPO | Linear pluggable optics: a DSP-less, replaceable transceiver that relies on the host for equalization. |
| CPO | Co-packaged optics: optical engines integrated next to the switch ASIC to minimize high-speed electrical reach. |
| OSFP-XD | An extended-density pluggable form factor with additional lanes for very high aggregate module bandwidth. |
| DR8 / 2×FR4 | Optical approaches using either eight parallel lanes or two wavelength-multiplexed four-lane groups for different fiber and reach requirements. |
| Silicon photonics | Optical components fabricated on silicon, enabling dense integration of modulators, waveguides and detectors. |
Final Take: The Optical System Matters as Much as Port Speed
1.6T Ethernet is arriving quickly because network bandwidth has become a direct input to accelerator utilization and return on investment. Yet the headline port speed is only half of the transition. The deeper change is optical: the industry is balancing the serviceability of DSP pluggables against the lower power of linear optics and the density of co-packaged photonics.
Infrastructure teams should prepare fiber, power, cooling and switching platforms for 1.6T while deploying it only where the topology and workload justify it. The strongest design will be the one that combines bandwidth with measured interoperability, repairability and observability—so GPUs keep computing instead of waiting on the network.
1.6T Ethernet Frequently Asked Questions
What is 1.6T Ethernet?
1.6T Ethernet is the Ethernet speed tier that delivers 1.6 terabits per second per port. It succeeds 800G and uses eight lanes of 200 Gb/s PAM4 signaling under the IEEE 802.3dj generation.
When will 1.6T Ethernet be widely available?
Early switches and optics appeared in 2025 and 2026. Broader AI data-center deployment is expected during 2026 and 2027 as standards, NICs, optics and switch platforms mature.
What is the difference between LPO and CPO?
Linear pluggable optics keeps a field-replaceable faceplate module but removes the module DSP to reduce power. Co-packaged optics places optical engines beside the switch ASIC for the lowest electrical loss and power, but with greater integration and serviceability tradeoffs.
How much power does a 1.6T optical transceiver use?
A DSP-based 1.6T pluggable is commonly estimated at roughly 25 to 30 watts, depending on vendor and reach. LPO and CPO target materially lower power per bit.
Why do AI data centers need 1.6T Ethernet?
Large AI training and inference clusters generate intense east-west traffic. 1.6T ports can create flatter fabrics with fewer links, optics and switch tiers, helping reduce latency and keep costly accelerators utilized.
Will copper cables still work at 1.6T?
Yes, for very short connections. Passive direct-attach copper at 200 Gb/s per lane is expected to reach roughly one to two meters, while active electrical cables can extend some in-rack links. Longer links generally require optics.